This disclosure relates to data processing.
In an example type of data processor known as an out of order processor, processor instructions are decoded and issued in their program order, but are allowed to be executed in a different order. The order of execution depends upon the inter-dependency of the instructions and whether source data (being the output of a previous instruction in the program code order) has become available as an input to an instruction awaiting execution.
To achieve this, the instructions are buffered before execution, for example in a buffer known as a reservation station. The architectural source and output registers relating to execution of the instruction are mapped to respective ones of a set of physical processor registers, for example using tags to indicate which physical registers relate to an instruction held at the buffer. As part of instruction issue circuitry, so-called wake-up logic detects, for buffered instructions, when the source operands become available, and “wakes up” or enables the corresponding instruction to be issued for execution.
The wake-up logic for a reservation station typically requires compare logic to match each source operand against the destination (output) registers for already-issued instructions, in order to detect when the relevant data becomes available. Wake-up logic can, in some examples, be a large contributor to power consumption due to the large number of comparators.